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Nama	Ukuran	Aksi
dw.h	1.49 MB	View DL Edit
edma.h	3.21 MB	View DL Edit
hsu.h	1.63 MB	View DL Edit
idma64.h	310 B	View DL Edit
imx-dma.h	3.39 MB	View DL Edit
ipu-dma.h	4.01 MB	View DL Edit
k3-event-router.h	317 B	View DL Edit
k3-psil.h	2.39 MB	View DL Edit
k3-udma-glue.h	5.38 MB	View DL Edit
mxs-dma.h	798 B	View DL Edit
pxa-dma.h	637 B	View DL Edit
qcom-gpi-dma.h	1.65 MB	View DL Edit
qcom_adm.h	227 B	View DL Edit
qcom_bam_dma.h	1.74 MB	View DL Edit
sprd-dma.h	8.2 MB	View DL Edit
ti-cppi5.h	33.04 MB	View DL Edit
xilinx_dma.h	1022 B	View DL Edit

Edit file: /usr/src/kernels/5.14.0-427.31.1.el9_4.x86_64/include/linux/dma/xilinx_dma.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Xilinx DMA Engine drivers support header file
 *
 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
 */

#ifndef __DMA_XILINX_DMA_H
#define __DMA_XILINX_DMA_H

#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>

/**
 * struct xilinx_vdma_config - VDMA Configuration structure
 * @frm_dly: Frame delay
 * @gen_lock: Whether in gen-lock mode
 * @master: Master that it syncs to
 * @frm_cnt_en: Enable frame count enable
 * @park: Whether wants to park
 * @park_frm: Frame to park on
 * @coalesc: Interrupt coalescing threshold
 * @delay: Delay counter
 * @reset: Reset Channel
 * @ext_fsync: External Frame Sync source
 * @vflip_en:  Vertical Flip enable
 */
struct xilinx_vdma_config {
	int frm_dly;
	int gen_lock;
	int master;
	int frm_cnt_en;
	int park;
	int park_frm;
	int coalesc;
	int delay;
	int reset;
	int ext_fsync;
	bool vflip_en;
};

int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
					struct xilinx_vdma_config *cfg);

#endif

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